1. Field of the Invention
The present invention relates to a cache memory that dynamically switches between low- and high-speed modes according to the frequency of a reference clock signal and a computer system employing the cache memory.
2. Description of the Prior
FIG. 1 shows an n-way set-associative cache memory according to a prior art. The cache memory has n ways of tag memories 100, n ways of data memories 101 provided for the tag memories 100, respectively, tag comparators 102 provided for the tag memories 100, respectively, a hit controller 103, and a way selector 104. FIG. 2 is a timing chart showing an operation of the cache memory to see if the cache memory holds required data. The operation is carried out according to a reference clock signal CLK. An index, which is a part of a reference address, is used to read a tag out of each tag memory 100. Each tag comparator 102 checks the read tag to see if it hits a cache address tag, which is the remaining part of the reference address. A result of the checking is supplied to the hit controller 103, which informs the way selector 104 of a hit tag memory whose tag has hit the cache address tag. The index of the reference address is also used to read data out of the n ways of data memories 101. Among the n pieces of read data, the way selector 104 selects one read out of the data memory that is associated with the hit tag memory.
Under a high-speed operation, the prior art simultaneously reads the tag memories 100 and data memories 101. In this case, the ways 0 to n-1 of the cache memory involve at least "n-1" mishits. This means that electric power used to read "n-1" extra data memories 101 is wasted whenever the cache memory is accessed.
To reduce power consumption, the prior art uses a technique of finding out a hit tag memory firstly, and then reading data out of a data memory associated with the hit tag memory. This technique, however, is slow in operation speed.
The prior art fixedly uses one of the above two techniques, or selectively uses them according to external instructions. In any case, it is difficult for the prior art to properly use the two techniques. It is required, therefore, to provide a technique of properly switching the above two techniques from one to another in a system such as a battery-driven portable terminal or a notebook computer that must have both a high-speed characteristic and a low power dissipation characteristic at low-speed operation.
As explained above, there are two prior art techniques for driving the n-way set-associative cache memory. One technique simultaneously reads the tag memories 100 and data memories 101 to realize a high-speed operation at the cost of large power consumption. The other reads a necessary one of the data memories 101 after the completion of checking all of the tag memories 100, to reduce power consumption at the cost of operation speed.
Instead of fixedly employing one of the above two techniques, it is required to properly and automatically switch the techniques from one to another according to the operating conditions of a system employing the cache memory.